Liquid crystal display apparatus

ABSTRACT

The invention is directed to a liquid crystal display apparatus comprising: a liquid crystal panel constructed by sandwiching a liquid crystal between a first transparent substrate having a plurality of data lines and a second transparent substrate having a plurality of scanning lines crossing the data lines; a data line driving integrated circuit connected to the plurality of data lines; and a scanning line driving integrated circuit for driving the plurality of scanning lines, wherein the data line driving integrated circuit is mounted on the first transparent electrode substrate, and the scanning line driving integrated circuit is mounted on the second transparent substrate, and wherein an swinging power supply integrated circuit for swinging a power supply potential of the scanning line driving integrated circuit while maintaining a constant amplitude in response to a liquid crystal driving AC signal is provided which is mounted directly on the first transparent substrate or on the second transparent substrate. This configuration serves to reduce the power consumption, size, and cost of the liquid crystal display apparatus, offers many advantages in design and fabrication, and enhances the reliability of the product.

TECHNICAL FIELD

[0001] The present invention relates to a liquid crystal displayapparatus having a plurality of scanning lines and a plurality of datalines arranged in a matrix array and, more particularly, to a liquidcrystal display apparatus in which a power supply generating circuitemploying an swinging power supply method which performs driving byswinging a power supply of a scanning line driving circuit isconstructed as an integrated circuit and disposed in the vicinity of thescanning line driving circuit, and also to the circuit configuration ofthe swinging power supply generating circuit.

BACKGROUND ART

[0002] In recent years, with the development of the information society,matrix-addressed display apparatuses have come to be used in a widerange of applications, such as televisions, PC monitors, navigationdisplay apparatuses, projection display apparatuses, head-up displayapparatuses, and telephone display apparatuses.

[0003] For example, EL (electroluminescence) display apparatuses andliquid crystal display apparatuses exemplified by passive addressingliquid crystal display apparatuses or active addressing (TFT, MIM, orTFD) liquid crystal display apparatuses are used as matrix-addresseddisplay apparatuses in a variety of fields. In particular, liquidcrystal display apparatuses, because of their advantages of small size,thin construction, light weight, low power consumption, etc., areprevalent in the field of small- and medium-size displays to such adegree that no other display apparatuses, including plasma displayapparatuses, can rival them.

[0004] While display apparatuses that use liquid crystals or ELmaterials have various advantages such as small size, thin construction,light weight, and low power consumption as just described, the realityis that these advantages are not fully used, as will be explained below.

[0005]FIG. 17 is a block diagram showing an essential portion of oneexample of a conventional art liquid crystal display apparatus. Asshown, the liquid crystal display apparatus 10 comprises a data linedriving circuit 17 for driving data lines 11, and a scanning linedriving circuit 15 for driving scanning lines 13 which are arranged atright angles to the data lines.

[0006] As shown, a power supply voltage of 3.0 V is supplied to astep-up circuit 171 and a power supply circuit 170 as well as to thescanning line driving circuit 15; the supply voltage is also supplied toa reference voltage generating circuit 173 and the data line drivingcircuit 17. The step-up circuit 170 supplies a power supply voltage V0to the power supply circuit 170, which in turn supplies scanning linedriving power supply voltages VDD and VSS to the scanning line drivingcircuit 15 to which is also supplied a driving reference voltage VM fromthe reference voltage generating circuit 173. Further, a control signalis input from an LCD controller (not shown). Based on these supplyvoltages and the control signal, a driving signal for driving thescanning lines is applied to the scanning lines.

[0007] The data line driving circuit 17, to which the power supplyvoltage of 3.0 V (also called the data line driving DC voltage) issupplied, is also supplied with the control signal and data signal fromthe LCD controller (not shown). The data lines are driven using thesesupply voltages and a timing signal.

[0008] For liquid crystal display apparatuses of such a construction,since portability is an important requirement, further reduction of sizeis demanded from the market, while at the same time, there is a need toincrease the display area for better viewability. While increasing thedisplay area within the limited space is strongly demanded, theperipheral area of the display area is becoming increasingly smallerbecause of the reduction of size.

[0009] In the illustrated prior art example, the scanning line drivingcircuit 15 and the data line driving circuit 17, arranged at theperiphery of the liquid crystal display apparatus 10, are eachconstructed from an integrated circuit employing a chip-on-glassstructure (hereinafter called COG) in which the IC chip is mounteddirectly on a transparent substrate. Accordingly, in the construction ofthe illustrated example, the overall size of the display apparatus canbe reduced by making the integrated circuits smaller and therebyreducing the peripheral area.

[0010] In one method of further reducing the peripheral area where theIC chips are mounted, it is required that the scanning line drivingcircuit 15 and the data line driving circuit 17 be further reduced insize; one way to achieve this is to further reduce the device size(smaller size and higher packing density) by reducing the maximumvoltage of the integrated circuits.

[0011] FIGS. 18(A) and 18(B) are driving waveform timing charts of theprior art construction. FIG. 18(A) is a timing chart for the scanningline driving signal, and FIG. 18(B) is a timing chart for the data linedriving signal. According to the IAPT method (six-level driving method)used in the prior art, the potential is varied for AC operation of theliquid crystal, as shown; that is, the scanning line driving circuit 15outputs a combination of V1 and V2 and a combination of V3 and V4,synchronized to which the data line driving circuit 17 outputs acombination of V5 and V4 and a combination of V1 and V6. Accordingly,the scanning line driving circuit 15 and the data line driving circuit17 are both required to have a breakdown voltage greater than thepotential difference between the highest potential level V1 and thelowest potential level V4 (that is, V1-V4), and therefore, high-voltageintegrated circuits had to be used.

[0012] That is, in the above method, the data line driving circuit 17also has had to be constructed from a high-voltage device, and has notbeen suitable in terms of the size and the packing density. The priorart method also has had the problem that high-speed operation of thedata line driving circuit 17, that becomes necessary to accommodate anincrease in the number of data signals when the number of pixels isincreased, cannot be achieved. A further problem has been that the powerconsumption increases because of the high-speed, high-voltage operation.

[0013] Furthermore, as the pixel pitch decreases and the number ofelectrode patterns increases as seen in recent liquid crystal displayapparatuses, the performance of the liquid crystal cannot be fullyutilized unless the driving voltage is increased with the increase inthe number, n, of columns in the matrix. A high AC voltage or ACamplitude is needed to increase the contrast, raise the transmissionbrightness, and achieve proper grayscale display; as a result, circuitryincluding the power supply circuit for driving the liquid crystal mustbe designed with lower voltage and reduced size.

[0014] For example, to increase the contrast and achieve hightransmission brightness, a high AC voltage or AC amplitude is needed fordriving the liquid crystal, and a push-pull driving technique is usedfor an output circuit for driving the liquid crystal. One example ofliquid crystal driving using the push-pull driving method is disclosedin Society of Display Bulletin Vol. 26/1, '85, pp. 9-15. In thispush-pull driving method, two voltage generating circuits whose ACamplitudes are opposite in polarity are provided, and the liquid crystaldevice is driven by the difference between the two voltages, producing amaximum driving voltage two times as high as the power supply voltage.However, this method has had the problem that when the driving voltageof the push-pull circuit is high, if the timing of switching between thetransistors connected in a push-pull configuration is displaced, a largeshoot-through current flows, resulting in an increase in the powerconsumption of the liquid crystal driving circuit.

[0015] One driving method that solves the above-enumerated problems usesan swinging power supply method disclosed, for example, in JapaneseUnexamined Patent Publication No. S60-249191 (U.S. Pat. No. 4,843,252)or Japanese Unexamined Patent Publication No. H2-282788 (U.S. Pat. No.5,101,116) previously filed by the Applicant. That is, as described inthe above Patent Publication, the Applicant proposed a circuit that doesnot require the use of a high-voltage IC, by employing a techniquecalled the “swinging power supply method” which can obtain a drivingoutput having a potential difference greater than the supply voltage, bycreating second pulse signals having a different reference voltage levelfrom a pulse generating signal using a clamping circuit and synthesizingthem, and which does not have a potential difference greater than thesupply voltage at the same point along the time axis.

[0016]FIG. 19 is a driving waveform diagram for explaining the swingingpower supply method employed in the conventional art. The diagram showsthe state of the power supply potential according to the swinging powersupply method. As shown, the power supply (high potential power supply)VDD to be input to the positive side power supply of the scanning linedriving circuit 15 is switched between VC and VD in synchronism with apulse generating signal, while the power supply (low potential powersupply) VSS to be input to the negative side power supply of thescanning line driving circuit 15 is switched between VA and VB insynchronism with the pulse generating signal. This driving method allowsthe breakdown voltage of the data line driving circuit 17 to be greatlyreduced without increasing the breakdown voltage of the scanning linedriving circuit 15, and achieves faster operation, higher packingdensity, and lower power consumption of the data line driving circuit 17to provide for an increase in the number of data signals.

[0017] However, when driving the scanning line driving circuit 15 usingthe prior art swinging power supply method described above, the highpotential power supply VDD and the low potential power supply VSS mustbe generated as shown in the figure. The high potential power supply VDDand the low potential power supply VSS (hereinafter, VDD and VSSsometimes referred to collectively as the “swinging power supply”) aregenerated from the power supply circuit 170 shown in FIG. 17. Asdescribed earlier, the power supply circuit 170 is supplied with the DChigh voltage V0, output from the step-up circuit 171, as well as thepower supply voltage of 3.0 V and ground potential (GND). Based on thesevoltages, the power supply circuit 170 generates the desired swingingpower supply voltages VDD and VSS.

[0018]FIG. 20 is a circuit diagram showing one example of the powersupply circuit 170 of FIG. 17; a basic circuit for generating theswinging power supply is shown here. A further detailed configuration ofthe circuit is given in FIG. 22 to be described later.

[0019] As shown in FIG. 20, the power supply circuit 170 comprises afirst circuit 200 and a second circuit 201. The first circuit 200 is apulse amplifying circuit, which converts the input pulse signal into ahigh-voltage pulse of amplitude V0. In the first circuit 200, a PMOSfield-effect transistor (PMOS-FET) 205 and an NMOS field-effecttransistor (NMOS-FET) 206 are connected in a push-pull circuitconfiguration using the DC high voltage V0 and GND as the powersupplies, and the pulse signal is supplied to the gate of the PMOS-FET205 via a clamping circuit 212 which comprises a capacitor 202, aresistor 203, and a diode 204. The clamping circuit 212 operates so asto clamp the high level of the pulse signal to the potential of thehigh-voltage V0. On the other hand, the pulse signal is supplieddirectly to the gate of the NMOS-FET 206. With this arrangement, thehigh voltage pulse amplified to V0 at the high level is output from thefirst circuit 200 at the timing inverted relative to the pulse signal,and is input to the second circuit 201.

[0020] The second circuit 201 is a circuit that generates the swingingpower supply voltages VDD and VSS from the input high voltage pulse. Inthe second circuit 201, one terminal of a capacitor 208 and one terminalof a capacitor 209 are connected in common to the output of the firstcircuit 200. The other terminal of the capacitor 208 is connected to thecathode of a diode 207 whose anode is coupled to the power supplyvoltage of 3.0 V; the cathode terminal is further connected to oneterminal of a capacitor 211, and the high potential swinging powersupply voltage VDD is thus output. The other terminal of the capacitor209 is connected to the anode of a diode 210 whose cathode is coupled toGND. The anode terminal of the diode 210 is further connected to theother terminal of the capacitor 211, and the low potential swingingpower supply voltage VSS is thus output.

[0021] In the second circuit 201, the DC component of the high voltagepulse input from the first circuit 200 is removed by the capacitors 208and 209, and the respective levels are clamped by the diodes 207 and 210to produce the respective outputs. The diode 210 is connected so thatthe swinging power supply VSS is clamped at the high potential side tothe GND level, while the diode 207 is connected so that the swingingpower supply VDD is clamped, at the low potential side, to the supplyvoltage of 3.0 V.

[0022] In this way, the second circuit 201 generates the high potentialand low potential swinging power supply voltages, the oscillation powersupplies VDD and VSS varying with the amplitude of the high potential insynchronism with the pulse signal while maintaining its potentialdifference constant. The high potential and low potential swinging powersupply voltages VDD and VSS thus generated by the power supply circuit170 are supplied to the scanning line driving circuit 15 mounted in theliquid crystal display apparatus 10. Therefore, in the prior artswinging power supply method, all the devices constituting the scanningline driving circuit 15 must be constructed from high-voltage devices.

[0023] However, in the scanning line driving circuit 15, the onlysection that actually needs to be constructed from a high-voltage deviceis the output driver section that drives the liquid crystal device.Accordingly, the scanning line driving circuit 15 in which all theconstituent devices are constructed from high-voltage devices has notbeen sufficient to achieve a small-size and low-power-consumptiondesign.

[0024] In view of this, the Applicant further studied the swinging powersupply method and, by noting that most of the circuit elements of thescanning line driving circuit 15 need not be constructed fromhigh-voltage devices, aimed at reducing the size of the scanning linedriving circuit 15 by constructing all the elements, other than theoutput driver, from low-voltage devices.

[0025]FIG. 21 is a diagram for explaining the state of the power supplypotential according to an swinging power supply method in which a powersupply for driving the low-voltage devices is added in the prior artcircuit configuration of FIG. 20. The high potential power supply (VDD)and the low potential power supply (VSS) are the same in operation asthose already described. The newly added low potential power supply(VCC) to be input to the scanning line driving circuit 15 is alsoswitched between VE and VF in synchronism with the low potential powersupply (VSS). In this way, the scanning line driving circuit 15 can bedriven without destroying the circuits therein constructed fromlow-voltage devices.

[0026]FIG. 22 shows one example of the circuit configuration forgenerating the power supply voltages according to the swinging powersupply method shown in FIG. 21. The configuration shown here issubstantially the same as that previously shown in FIG. 20, except that,in the example shown here, VDL, VSL, the reference signal, etc. areinput and VCC is output.

[0027] In FIG. 22, VDL is a system power supply, VSL is system ground(GND), V0 is a high-voltage power supply, and VD2 (that is, a DC voltageof 3.0 V) is a liquid crystal driving voltage to the data line drivingcircuit 17. The reference signal is a signal having a level intermediatebetween VDL and VSL, and it determines the period A and the period B inFIG. 21.

[0028] The configuration and operation of FIG. 22 will be describedbelow, though the description may partially overlap with that of thecircuit operation of FIG. 20. In FIG. 22, reference numerals 223 and 230are PMOS-FETs, and 224 is an NMOS-FET. Further, 221, 228, and 229 arediodes, 222 is a resistor, and 220, 225, 226, and 227 are capacitors.

[0029] As shown, the reference signal is input to the capacitor 220, andthe signal clamped to V0 by the clamping circuit 212 constructed withthe capacitor 220, diode 221, and resistor 222 is supplied to the gateof the PMOS-FET 223. The reference signal is further input directly tothe gate of the PMOS-FET 230 as well as to the NMOS-FET 224. With thePMOS-FET 223 and NMOS-FET 224 being switched based on the high level andlow level of the reference signal, a voltage switching between the highpotential V0 and low potential VSL is supplied to the capacitors 225,226, and 227 connected to the output side of the push-pull circuit.

[0030] The diode 228 is connected to the other terminal of the capacitor225, and VDD, clamped to VD2, is thus output. The diode 229 is connectedto the other terminal of the capacitor 227, and VSS, clamped to VSL, isthus output. The drain of the PMOS-FET 230 is connected to one terminalof the capacitor 226, and VCC, clamped to VDL, is output in synchronismwith the reference signal. With this circuit configuration, the powersupply, according to the swinging power supply method, shown in FIG. 21can be generated.

[0031] However, the power supply generating circuit according to theconventional art swinging power supply method such as shown in FIGS. 20and 22 has the following problems. That is, as all the components of theprior art power supply generating circuit are separate components(discrete components) such as transistors, diodes, resistors,capacitors, etc., the configuration has not been sufficient to achievesmaller size, lower power consumption, and higher versatility whileutilizing the advantage of the swinging power supply method.

[0032] That is, to generate the swinging power supply with thesediscrete components, a circuit board for the power supply generatingcircuit has had to be provided separately, and this circuit board hasbeen a bottleneck preventing further size reduction when designing theproduct. Furthermore, as the liquid crystal driving voltage is 20 V to40 V, it has been necessary to use high-voltage components, whichnecessarily means using large-size components, and hence a problem, thatthe circuit area further increases, occurs.

[0033] Besides, the circuit board for the power supply generatingcircuit has had to be arranged separately from the liquid crystaldisplay panel (which corresponds to the liquid crystal display apparatus10 in FIG. 17). As a result, when the manufacturer of the liquid crystaldisplay panel is different from the designer of the liquid crystaldisplay apparatus as the end product, there has often occurred theproblem of malfunctioning due to mismatch in the specification of theswinging power supply. This problem has been solved by having themanufacturer of the liquid crystal display panel also prepare thecircuit diagram of the power supply generating circuit. However, thishas not only increased the burden of the manufacturer, but also limitedthe freedom of design of the end product, a factor preventing furtherreductions in cost and size. Thus, the power supply generating circuitaccording to the prior art swinging power supply method has had a majoreffect on the versatility of the liquid crystal display panel, includingsize reduction.

DISCLOSURE OF THE INVENTION

[0034] Accordingly, the present invention is directed to the provisionof a liquid crystal display apparatus by solving the above-enumeratedproblems, and the basic point of the invention is to construct theswinging power supply circuit in integrated circuit form by avoidingvarious technical problems and to mount the integrated circuit in theliquid crystal display apparatus.

[0035] According to the present invention, there is provided a liquidcrystal display apparatus comprising: a liquid crystal panel constructedby sandwiching a liquid crystal between a first transparent substratehaving a plurality of data lines and a second transparent substratehaving a plurality of scanning lines crossing the data lines; a dataline driving integrated circuit connected to the plurality of datalines; and a scanning line driving integrated circuit for driving theplurality of scanning lines, wherein

[0036] the data line driving integrated circuit is mounted on the firsttransparent electrode substrate, and the scanning line drivingintegrated circuit is mounted on the second transparent substrate, andwherein an swinging power supply integrated circuit for swinging a powersupply potential of the scanning line driving integrated circuit whilemaintaining a constant amplitude in response to a liquid crystal drivingAC signal is provided which is mounted directly on the first transparentsubstrate or on the second transparent substrate.

[0037] In a preferred embodiment, the swinging power supply integratedcircuit is constructed from a single chip, and is mounted directly onthe second transparent substrate.

[0038] In a preferred embodiment, the swinging power supply integratedcircuit takes as inputs the liquid crystal driving AC signal and anoutput of a step-up circuit that defines the amplitude of the swingingpower supply.

[0039] In a preferred embodiment, the swinging power supply integratedcircuit comprises: three output block circuits consisting of a firstoutput block circuit, a second output block circuit, and a third outputblock circuit; and one discharge block circuit, wherein

[0040] the first output block circuit comprises: a level shift circuitwhich converts the amplitude of an externally supplied reference signalinto a prescribed amplitude; a first logic circuit which controls thetiming of the reference signal whose level has been converted by thelevel shift circuit; and a first output driver circuit which delivers anoutput of the first logic circuit,

[0041] the second output block circuit comprises: a second logic circuitwhich controls the timing of the reference signal; and a second outputdriver circuit which outputs a value of the second logic circuit,

[0042] the third output block circuit comprises: a clamping circuitwhich clamps the reference signal; and a third output driver circuitwhich outputs the value of the clamping circuit, and

[0043] the discharge block circuit comprises: a detection circuit whichdetects the system power supply being turned off; and a dischargecircuit which short-circuits the third output driver circuit by a signaldetected by the detection circuit.

[0044] In a preferred embodiment, the swinging power supply integratedcircuit comprises: three output block circuits consisting of a firstoutput block circuit, a second output block circuit, and a third outputblock circuit; and one discharge block circuit, wherein

[0045] the first output block circuit comprises: a level shift circuitwhich converts the amplitude of an externally supplied reference signalinto a prescribed amplitude; a first logic circuit which controls thetiming of the reference signal whose level has been converted by thelevel shift circuit; and a first output driver circuit constructed froman inverter whose gate is connected to a signal output from the firstlogic circuit,

[0046] the second output block circuit comprises: a second logic circuitwhich controls the timing of the reference signal; and a second outputdriver circuit constructed from an open-drain circuit of a firstPMOS-FET whose gate is connected to a signal output from the secondlogic circuit,

[0047] the third output block circuit comprises: a clamping circuitwhich clamps the reference signal; and a third output driver circuitconstructed from an open-drain circuit of a second PMOS-FET whose gateis connected to a signal output from the clamping circuit, and

[0048] the discharge block circuit comprises: a detection circuit whichdetects a system power supply being turned off; and a discharge circuitwhich short-circuits the third output driver circuit by a signaldetected by the detection circuit.

[0049] In a preferred embodiment, the clamping circuit has aconfiguration such that one end of a capacitor is connected to thesupplied reference signal and the other end thereof is connected to acathode of a first diode, one end of a first resistor, and the gate ofthe second PMOS-FET, while an anode of the first diode and the other endof the first resistor are connected to a source and the bulk of thesecond PMOS-FET.

[0050] In a preferred embodiment, the discharge block circuit has acircuit configuration such that a source and a bulk of a third PMOS-FETare connected to a source and a bulk of the first PMOS-FET, a gate ofthe third PMOS-FET is connected to a source and a bulk of the secondPMOS-FET, and a drain of the third PMOS-FET is connected to a secondresistor and a gate of a fourth PMOS-FET, while a source and a bulk ofthe fourth PMOS-FET are connected to the source and the bulk of thesecond PMOS-FET and a drain of the fourth PMOS-FET is connected to athird resistor whose one end is connected to the second resistor and adrain of the second PMOS-FET.

[0051] In a preferred embodiment, the first output block circuitcomprises a plurality of PMOS-FETs and a plurality of NMOS-FETs, and anoutput selection circuit, having a function that can always turn offpart of the plurality of PMOS-FETs and part of the plurality ofNMOS-FETs by an external output setting terminal independently of thereference signal, is provided at a gate input of each of the PMOS-FETsand the NMOS-FETs.

[0052] With the above configuration, the present invention offersvarious effects as enumerated below.

[0053] As the liquid crystal display apparatus can be designed byincorporating the swinging power supply integrated circuit at the timeof designing the product, freedom in specification at the time ofproduct design can be greatly enhanced. In the conventional art swingingpower supply generating circuit which was constructed with discretecomponents and connected to the liquid crystal display apparatus afterassembling them on a separate circuit board this inhibited the freedomof product design as a whole.

[0054] As will be described later, as the scanning line driving circuit,the data line driving circuit, and the swinging power supply integratedcircuit can be interconnected over an FPC board, the wiring can begreatly simplified.

[0055] As the swinging power supply circuit is implemented in integratedcircuit form and mounted in the liquid crystal display panel, theoverall noise of the liquid crystal display apparatus can be reduced.

[0056] As the swinging power supply circuit is implemented in integratedcircuit form and mounted in the liquid crystal display panel, the numberof components can be greatly reduced, as a result of which fabricationman-hours and fabrication costs can be reduced while greatly improvingstability in fabrication.

[0057] As the swinging power supply circuit is implemented in integratedcircuit, the power consumption of the liquid crystal display apparatuscan be reduced, while also reducing the overall size and weight of theproduct.

[0058] Further, as will be described in detail later, as the outputimpedance of each driver can be easily changed by means of a settingterminal, the output impedance of the driver can be set that matches thesize of the liquid crystal display panel; furthermore, if power is cutoff during the selection operation of the scanning line driving circuit,the discharge circuit acts to prevent the DC component from beingcontinuously applied.

[0059] In a specific configuration, the swinging power supply integratedcircuit employing the swinging power supply method and implemented inintegrated circuit form is mounted (by means of COG) on the samesubstrate as the scanning line driving circuit and in the vicinity ofthe scanning line driving circuit, as will be described later.

BRIEF DESCRIPTION OF THE DRAWINGS

[0060]FIG. 1 is a diagram showing the basic construction of a liquidcrystal display apparatus according to one embodiment of the presentinvention.

[0061]FIG. 2 is a block diagram showing an essential portion ofperipheral circuitry for driving the basic construction of FIG. 1.

[0062]FIG. 3 is a basic circuit diagram of an swinging power supplyintegrated circuit according to the invention of FIG. 1.

[0063]FIG. 4 is a timing chart showing driving waveforms for the liquidcrystal display apparatus of FIG. 1.

[0064]FIG. 5 is a cross-sectional view of an essential portion forexplaining the connection structure of the swinging power supplyintegrated circuit of FIG. 1.

[0065]FIG. 6 is a block diagram showing the configuration of oneembodiment of the swinging power supply integrated circuit according tothe present invention.

[0066]FIG. 7 is a diagram for explaining the relationship between powersupply voltages supplied to the swinging power supply integrated circuitof FIG. 6.

[0067]FIG. 8 is a circuit diagram showing one example of a level shiftcircuit forming part of a first output block circuit in theconfiguration of FIG. 6.

[0068]FIG. 9 is a circuit diagram showing one example of a first outputdriver circuit forming part of the first output block circuit in theconfiguration of FIG. 6.

[0069]FIG. 10 is a circuit diagram showing one example of a secondoutput driver circuit forming part of a second output block circuit inthe configuration of FIG. 6.

[0070]FIG. 11 is a circuit diagram showing one example of a clampingcircuit forming part of a third output block circuit in theconfiguration of FIG. 6.

[0071]FIG. 12 is a circuit diagram showing one example of a third outputdriver circuit forming part of the third output block circuit in theconfiguration of FIG. 6.

[0072]FIG. 13 is a block diagram showing external capacitors connectedto the swinging power supply integrated circuit of the configurationshown in FIG. 6.

[0073]FIG. 14 is a diagram showing the swinging power supply waveformsgenerated by the swinging power supply integrated circuit of theconfiguration shown in FIG. 6.

[0074]FIG. 15 is a circuit diagram showing one example of a dischargecircuit in the configuration of FIG. 6.

[0075]FIG. 16 is a circuit diagram showing one example of a first logiccircuit and the first output driver circuit forming the first outputblock circuit in the configuration of FIG. 6.

[0076]FIG. 17 is a diagram showing a liquid crystal display apparatusaccording to the conventional art.

[0077] FIGS. 18(A) and 18(B) are timing charts illustrating basicdriving waveforms for the prior art liquid crystal display apparatusshown in FIG. 17.

[0078]FIG. 19 is a basic waveform diagram illustrating driving waveformsfor the liquid crystal display apparatus of FIG. 17 employing answinging power supply method according to the prior art.

[0079]FIG. 20 is a basic circuit diagram of a conventional art swingingpower supply circuit used in FIG. 17.

[0080]FIG. 21 is a diagram for explaining the state of power supplypotential according to a conventional art swinging power supply methodin which a power supply for driving low-voltage devices is added.

[0081]FIG. 22 is a diagram showing one example of a circuit forgenerating power supply voltages according to the prior art swingingpower supply method.

BEST MODE FOR CARRYING OUT THE INVENTION

[0082] The preferred embodiments using the liquid crystal displayapparatus of the present invention will be described below withreference to the accompanying drawings.

[0083]FIG. 1 is a diagram showing the basic construction of the liquidcrystal display apparatus according to one embodiment of the presentinvention. A liquid crystal display panel 10 is constructed bylaminating an upper glass substrate 16, on which data lines 11 made oftransparent electrodes of ITO are formed, to a lower glass substrate 14,on which scanning lines 13 made of transparent electrodes of ITO areformed, and by bonding the two substrates together using a sealingmember.

[0084] A liquid crystal is sandwiched between the lower glass substrate14 and the upper glass substrate 16, and each glass substrate is coatedwith an alignment film (not shown) to align the liquid crystal moleculesin the desired direction. A data line driving circuit 17 for driving thedata lines 11 is mounted on the lower glass substrate 14 using a COG(chip-on-glass) technique. Likewise, a scanning line driving circuit 15is mounted on the upper glass substrate 14 using the COG technique, andis electrically connected to the scanning lines 13.

[0085] In this embodiment of the invention, an swinging power supplyintegrated circuit 18, which is an integrated circuit (IC)implementation of a power supply generating circuit for generating answinging power supply, is also mounted on the lower glass substrate 14using the COG technique. Accordingly, input/output terminals of theswinging power supply integrated circuit 18 are electrically connectedto the ITO formed on the lower glass substrate 14.

[0086] The COG mounting essential to the implementation of the swingingpower supply integrated circuit 18 of the present invention will bedescribed first with reference to FIG. 5.

[0087]FIG. 5 is a cross-sectional view of an essential portion forexplaining the connection structure of the swinging power supplyintegrated circuit 18 of FIG. 1. More specifically, the cross-sectionalview shows the essential portion where the swinging power supplyintegrated circuit 18 of FIG. 1 is mounted using the COG technique. InFIG. 5, bump electrodes 51 are formed on the swinging power supplyintegrated circuit 18. In the present embodiment, each bump electrode 51is formed from Au. The bump electrodes may be formed from otherelectrically conductive materials. The bump electrode 51 is electricallyconnected to the lower glass substrate 14 via an anisotropic conductivefilm (hereinafter abbreviated as ACF). The ACF comprises conductiveparticles 52 and a thermosetting non-conductive adhesive material 53;when the swinging power supply integrated circuit 18 is pressed underheat in the direction indicated by arrow, the bump electrode 51 ispressed against the conductive particles 52 which are crushed to providean electrical connection to the ITO wiring 55 formed on the lower glasssubstrate 14 and, in this condition, the adhesive material 53 is curedto maintain the connection. Here, conductive particles coated with thininsulating films (not shown) may be used instead of the conductiveparticles 52.

[0088] In the COG mounting of the swinging power supply integratedcircuit 18 on the lower glass substrate 14 described above, theinput/output terminals and power supply terminals of the scanning linedriving circuit 15, data line driving circuit 17, and swinging powersupply integrated circuit 18 in FIG. 1 are electrically connected on therespective glass substrates to a flexible printed circuit board(hereinafter abbreviated as FPC) 19 via the ITO wiring formed on therespective glass substrates.

[0089] Usually, in the fabrication of the FPC 19, wiring patterns areformed using copper foil on both surfaces of a substrate made of a150-μm thick polyimide base material, and the wiring patterns on bothsurfaces are interconnected at suitable places via through-holes tocomplete the circuit wiring. Using such wiring patterns, the powersupply and control signal lines common to the scanning line drivingcircuit 15, data line driving circuit 17, and swinging power supplyintegrated circuit 18 in FIG. 1 are wired over the FPC 19 in such amanner as to minimize the number of external connection terminals.

[0090] Next, referring to FIGS. 1 and 2, the wiring on the FPC 19 willbe described below in the order of the external connection terminalsarranged on the FPC 19. The first terminal is for providing a powersupply voltage of 3.0 V, which is used as a logic power supply for thescanning line driving circuit 15, a clamping power supply for theswinging power supply integrated circuit 18, and a logic power supplyand data line driving power supply for the data line driving circuit 17.The second terminal is used as ground (GND), and is connected to the GNDterminal of each of the above-listed power supply terminals. The thirdterminal is for a driving reference power supply VM which provides thereference voltage for the liquid crystal driving voltage and is suppliedto the scanning line driving circuit 15.

[0091] The fourth terminal is for a control signal; the control signalcomprises a group of three signals, that is, a latch pulse LP whichprovides scan timing, a frame signal FR which provides frame timing, anda clock pulse CP which provides timing for transferring a data signalDATA to the data line driving circuit 107. In FIG. 1, these signals arecollectively shown as the “control signal”. The FPC 19 supplies therespective control signals, i.e., the latch pulse LP to the scanningline driving circuit 15 and the data line driving circuit 17, the framesignal FR to the scanning line driving circuit 15, and the clock pulseCP to the data line driving circuit 17.

[0092] The fifth terminal is for a timing signal DF which providespolarity inversion timing for the liquid crystal, and which is suppliedto the scanning line driving circuit 15, swinging power supplyintegrated circuit 18, and data line driving circuit 17. The sixthterminal is an input terminal V0 of a high-voltage DC power supply fordriving the liquid crystal, which is supplied to the swinging powersupply integrated circuit 18. The seventh terminal is a DATA terminalwhich is connected to the data line driving circuit 17 to transfer imagedata. The eighth terminal is a power supply terminal for a highpotential supply voltage VDD, and the ninth terminal is for a lowpotential power supply voltage VSS; these voltages are supplied from theswinging power supply output terminals of the swinging power supplyintegrated circuit 18, and delivered as the VDD power supply and the VSSpower supply, respectively, to the scanning line driving circuit 15.

[0093] As described above, the terminals connecting to the respectivecircuits 15, 17, and 18 are arranged on the FPC 19 so as to minimize thenumber of external connection terminals. Reducing the number ofterminals not only serves to reduce the overall size of the apparatus,but also offers such effects as reducing the cost of connectors,simplifying the connection work, and improving the connectionreliability. In the present embodiment, the respective circuits areinterconnected via the FPC 19 by mounting the swinging power supplyintegrated circuit 18 on the lower glass substrate 14 by means of COG asdescribed above.

[0094]FIG. 2 is a block diagram showing an essential portion ofperipheral circuitry for driving the basic construction of FIG. 1. Areference voltage generating circuit 21, a step-up circuit 22, acapacitor 23, etc. are connected to the construction illustrated inFIG. 1. The power supply voltage of 3.0 V is provided to the referencevoltage generating circuit 21 and the step-up circuit 22 as well as tothe corresponding terminal of the FPC 19, while the control signal (thelogic signal group consisting of the scan timing signal, frame signal,data latch timing, etc. as earlier described), the data signal, the DFsignal, etc. are supplied to the respective terminals of the FPC 19.

[0095] The DF signal as the liquid crystal driving AC signal is suppliedto the DF terminal of the FPC 19, the data signal as the image data issupplied to the DATA terminal of the FPC 19, the output V0 of thestep-up circuit 22 is supplied to the V0 terminal of the FPC 19, and theoutput VM of the reference voltage generating circuit 21 is connected tothe VM terminal of the FPC 19. The grounds of the reference voltagegenerating circuit 21 and the step-up circuit 22 are connected to theGND terminal of the FPC 19. The multilayer ceramic capacitor 23 with acapacitance of 1 μF is connected between the VDD terminal and VSSterminal of the FPC 19.

[0096] The operation of each circuit block will be described below. Thereference voltage generating circuit 21 is a circuit for generating thereference voltage VM for the driving voltage of the liquid crystaldisplay panel 10, and generates a DC voltage of 3.0 V to 1.5 V using aseries regulator. Instead of the series regulator, a switching capacitortype or a step-down switching regulator or the like can be used togenerate the required voltage, but the present embodiment employs aseries regulator which can be constructed with the fewest number ofcomponents.

[0097] The step-up circuit 22 is a circuit for generating the DC highvoltage V0 from the power supply voltage of 3.0 V, and is constructedfrom a step-up switching regulator. In the present embodiment, thestep-up circuit 22 incorporates a liquid crystal temperaturecompensating circuit (not shown), and is designed to output 20 V at roomtemperature with a temperature coefficient of −0.4V/° C. Various methodsare proposed for the construction of a circuit comprising a combinationof a temperature compensating circuit and a switching regulator; in thepresent embodiment, the circuit is implemented by using a thermistor forthe output voltage dividing resistor of the switching regulator circuit.With this configuration, the output voltage V0 of the step-up circuit 22changes with temperature so that the liquid crystal display apparatus 10can always produce a display with optimum contrast. A switchingregulator is used as the step-up circuit 22, but if an increase in thenumber of components is permitted, a charge pump type step-up circuitmay be used.

[0098]FIG. 3 is a basic circuit diagram of the swinging power supplyintegrated circuit according to the invention of FIG. 1. As describedabove, the swinging power supply generating circuit according to thepresent invention is constructed, in an integrated circuit form, as theswinging power supply integrated circuit 18. That is, the power supplygenerating circuit for generating the swinging power supply from thesupply voltage of 3.0 V and the DC high voltage V0 is designed inintegrated circuit form and formed on a silicon substrate.

[0099] The operation of this circuit will be described below. A levelshift circuit is constructed using four FETs, i.e., a PMOS-FET 31, aPMOS-FET 33, an NMOS-FET 32, and an NMOS-FET 34.

[0100] As shown, the sources of the PMOS-FET 31 and PMOS-FET 33 areconnected to the power supply line of the DC high voltage V0, the gateof the PMOS-FET 31 is connected to the drain of the PMOS-FET 33, and thegate of the PMOS-FET 33 is connected to the drain of the PMOS-FET 31.Further, the drain of the NMOS-FET 32 is connected to the drain of thePMOS-FET 31, and the drain of the NMOS-FET 34 is connected to the drainof the PMOS-FET 33.

[0101] The sources of the NMOS-FET 32 and NMOS-FET 34 are connected toGND, the gate of the NMOS-FET 32 is connected to the input signal DF,and the gate of the NMOS-FET 34 is connected to the output of aninverter 37. The DF signal is coupled to the input of the inverter 37.The level shift circuit is constructed with the above connections, andthe DF signal that is input at GND to 3.0V levels is amplified andconverted into a signal having GND to V0 levels but identical in phaseto the DF signal.

[0102] An output buffer for outputting the swinging power supply VDD isconstructed by connecting a PMOS-FET 35 and an NMOS-FET 36 in aninverter configuration. The source of the PMOS-FET 35 is connected tothe power supply line of the DC high voltage V0, while the source of theNMOS-FET 36 is connected to the power supply line of the supply voltageof 3.0 V. The DF signal amplified and converted to the GND to V0 levels,and output from the level shift circuit, is supplied to the input of theoutput buffer. During the period that the supplied DF signal is at ahigh level, that is, the potential of V0, the NMOS-FET 36 is ON and thePMOS-FET 35 is OFF, so that 3.0 V is output as the VDD.

[0103] On the other hand, during the low level period in which the DFsignal takes the GND potential, the PMOS-FET 35 is ON and the NMOS-FET36 is OFF, so that the voltage of V0 is output as the VDD. In this way,in synchronism with the DF signal, the DC high voltage V0 and the powersupply voltage of 3.0 V are alternately selected for output as the VDD.This VDD is the positive side output of the swinging power supply.

[0104] In FIG. 3, a PMOS-FET 41 is a clamping transistor, which acts toadd DC potential to the AC voltage when the swinging power supply VDD iscapacitively coupled by an externally added capacitor. In theconstruction of the clamping circuit, the source of the PMOS-FET 41, thecathode of a diode 39, and one end of a resistor 40 are connected to theGND line, and the anode of the diode 39, the other end of the resistor40, and one end of a capacitor 38 are connected to the gate of thePMOS-FET 41. The other end of the capacitor 38 is coupled to the DFsignal.

[0105] The capacitor 38 is a MOS capacitor which is integrated on thesemiconductor integrated circuit, and is chosen to have a capacitance of470 pF. The resistor 40 is formed from polysilicon and is chosen to havea resistance of 2M to 5M Ω. These values must be chosen so that the timeconstant τ expressed by the product of the capacitance and theresistance value will become sufficiently longer than the switching timeof the swinging power supply. If it is shorter, the gate voltage of thePMOS-FET 41 drops and a sufficient ON resistance cannot be obtained. Thecircuit configuration of the swinging power supply integrated circuit 18has been described above.

[0106] The liquid crystal display apparatus of the present invention isimplemented by mounting the above-described swinging power supplyintegrated circuit 18 using the COG technique. The circuit describedabove is one example of the circuit for generating the swinging powersupply and, if one refers to this embodiment, one can implement thecircuit in like manner using a circuit configuration other than the onedescribed above. By implementing the circuit as a semiconductorintegrated circuit, the invention can be carried out in like manner asthe circuit can be mounted using the COG technique. Further, as long asit is implemented as a semiconductor integrated circuit, the circuit maybe constructed from multiple chips. However, from the standpoint ofreducing the cost and size, it is advantageous to construct the circuitfrom one chip as in the present embodiment.

[0107]FIG. 4 is a timing chart showing the driving waveforms for theliquid crystal display apparatus of FIG. 1. As the V0 terminal of theFPC 19 is connected to the output of the step-up circuit 22, 20 VDC isinput as V0. Further, 3.0 V and 0 V are input to the 3.0V and GNDterminals, respectively. The DF signal as the liquid crystal polarityinversion signal is input to the DF terminal; this signal is arectangular wave which is 3.3 V at high level and 0 V at low level.These are the waveforms at the input terminals.

[0108] As previously shown in FIG. 1, the power supply voltages V0, 3.0V, and GND and the DF signal, input at the respective input terminals ofthe FPC 19, are input to the swinging power supply integrated circuit18. Further, as shown in FIG. 3, the input DF signal is converted into arectangular wave that takes voltage levels of V0 and 0 V, by the levelshift circuit comprising the PMOS-FETs 31 and 33 and the NMOS-FETs 32and 34. The converted DF signal is input into the output buffer whichproduces the swinging power supply VDD by alternately selecting thevoltage levels of V0 and 3.0 V in synchronism with the DF signal. Theoutput waveform of this swinging power supply VDD is shown in FIG. 4.

[0109] When the DF signal is at the high level, VDD outputs 3.0 V, andwhen it is at the low level, VDD outputs 20 V as V0. Further, as shownin FIG. 2, the swinging power supply VDD is connected to the VSSterminal of the FPC 19 via the capacitor 23. This VSS terminal isconnected to the VSS terminal of the swinging power supply integratedcircuit 18, which means that the swinging power supply VDD is input tothe VSS terminal in FIG. 2 via the capacitor 23. As VDD is input via thecapacitor 23, an AC voltage produced by removing the DC component fromthe swinging power supply VDD is applied to the VSS terminal. On theother hand, the VSS terminal is also the drain output of the PMOS-FET41.

[0110] Here, when the DF signal is at a low level, the PMOS-FET 41 isON, and 0 V is applied to the VSS terminal. At this time, the potentialat the VSS terminal side of the capacitor 23 is charged to 0 V. As aresult, as shown in FIG. 4, during the low level period of the DFsignal, 0 V is output at the VSS terminal. Next, when the DF signal goesto the high level, the PMOS-FET 41 turns off. At the same time, thepotential of the swinging power supply VDD connected to the other sideof the capacitor 23 drops, by 17 V, from 20 V to 3.0 V.

[0111] As a result, the potential at the VSS terminal side of thecapacitor 23 also drops from 0 V to −17 V. Accordingly, as shown in FIG.4, the VSS terminal outputs 0 V during the low level period of the DFsignal, and −17 V during the high level period. This provides theswinging power supply VSS. As is apparent from FIG. 1, the oscillationpower supplies VDD and VSS are connected via the FPC 19 to the powersupply terminals of the scanning line driving circuit 15. The scanningline driving circuit 15 can thus be driven by the oscillation powersupplies.

[0112] According to the present embodiment, all the voltages input tothe respective power supply terminals of the FPC 19 are DC voltages, andthe capacitor 23 connected between VDD and VSS is constructed from aconventional ceramic capacitor. In this way, when viewed from theexternal circuits, it can be seen that the apparatus can be driven bysimple circuitry that just applies a DC low voltage and a DC highvoltage.

[0113] Further, as the need is eliminated for the external circuit boardas required in the conventional art swinging power supply method for thepower supply circuit constructed from discrete components, as previouslydescribed, drastic reductions in the cost and the size of the circuitboard can be achieved. Furthermore, as the swinging power supplyintegrated circuit 18 is mounted in the liquid crystal display apparatusby using the COG technique as previously described, the manufacturer cansupply the apparatus to the user by designing the liquid crystal paneland the swinging power supply circuit in optimum condition free fromtrouble such as malfunctions; therefore, the user need only prepare asimple DC power supply, and the liquid crystal display apparatus can bedriven using the swinging power supply method in exactly the same way asbefore.

[0114]FIG. 6 is a block diagram showing the configuration of oneembodiment of the swinging power supply integrated circuit 18 accordingto the present invention. Four kinds of power supply voltages, VSL, VDL,VD2, and V0, are input to the swinging power supply integrated circuit18 As previously described, VSL is system ground, VDL is a system powersupply, VD2 is a liquid crystal driving voltage to the data line drivingcircuit 17, and V0 is a high-voltage power supply based on which toproduce the swinging power supply. Here, VSL in FIG. 6 corresponds toGND in FIG. 3, and VDL and VD2 in FIG. 6 both correspond to 3 V in FIG.3. The detailed configuration of each block will be described below withreference to the figure.

[0115] In the figure, reference 61 indicates the reference signal; thelow level potential is VSL, and the high level potential is VDL. Thereference signal 61 in FIG. 6 corresponds to DF in FIG. 3. Referencenumeral 62 is a first output block circuit, 67 is a second output blockcircuit, and 71 is a third output block circuit. The reference signal 61is supplied to all the output block circuits.

[0116] Further, reference numerals 66, 70, 74, etc. indicate the outputsof the swinging power supply integrated circuit 18, that is, 66indicates the output (VDD) of the first output block circuit 62, 70 theoutput (VCC) of the second output block circuit 67, and 74 the output(VSS) of the third output block circuit 71. On the other hand, referencenumerals 76 and 77 indicate the output setting terminals of a firstlogic circuit 64, which are used within the circuit.

[0117] The first output block circuit 62 comprises three circuit blocks,i.e., a level shift circuit 63, the first logic circuit 64, and a firstoutput driver circuit 65.

[0118] The level shift circuit 63 (which corresponds to the level shiftcircuit (FETs 31, 32, 33, and 34) in FIG. 3) is a circuit that amplifiesand converts the signal levels VDL and VSL of the reference signal 61into the V0 and VSL levels, respectively.

[0119]FIG. 7 is a diagram for explaining the relationship between thepower supply voltages supplied to the swinging power supply integratedcircuit of FIG. 6. In general, the relations V0>VD2 and VDL>VSL hold. Asearlier described, when VSL is 0 V, then V0 is about 20 V, VD2 is about3.0 V, and VDL is about 2.7 V. However, the voltages shown here greatlyvary depending on the ambient temperature, the liquid crystal used, thesystem design of the liquid crystal display apparatus, etc.

[0120]FIG. 8 is a circuit diagram showing one example of the level shiftcircuit forming part of the first output block circuit in theconfiguration of FIG. 6. The circuit shown here is an alternativeexample of the level shift circuit contained in the previously describedcircuit of FIG. 3. Reference numerals 80 and 81 are inverters to whichthe power supply voltages VDL and VSL are input. The reference signal 61is also input to the inverter 80, whose output is connected to theinverter 81.

[0121] Reference numerals 83, 84, 85, and 86 are PMOS-FETs, and 87 and88 are NMOS-FETs. The bulk side of each of the PMOS-FETs is connected tothe power supply line of V0, and the sources of the PMOS-FETs 83 and 84are also connected to the power supply line of V0. The drain of thePMOS-FET 83 is connected to the source of the PMOS-FET 85, and the drainof the PMOS-FET 84 is connected to the source of the PMOS-FET 86.

[0122] The drain of the PMOS-FET 85 is connected to the gate of thePMOS-FET 86 as well as to the drain of the NMOS-FET 87, and the drain ofthe PMOS-FET 86 is connected to the gate of the PMOS-FET 85 as well asto the drain of the NMOS-FET 88. The source and bulk side of theNMOS-FETs 87 and 88 is connected to VSL.

[0123] The output of the inverter 81 is connected to the gates of thePMOS-FET 83 and NMOS-FET 87, while the output of the inverter 80 isconnected to the gates of the PMOS-FET 84 and NMOS-FET 88.

[0124] Reference numeral 82 indicates the output signal of the levelshift circuit 63. When the reference signal 61 is at VDL, the NMOS-FET87 is conducting and the NMOS-FET 88 is non-conducting, so that theoutput voltage 82 is V0. Conversely, when the reference signal 61 is atVSL, the NMOS-FET 87 is non-conducting and the NMOS-FET 88 isconducting, so that VSL is output as the output signal 82.

[0125] In this way, the level shift circuit 63 converts the VDL/VSLamplitude of the reference voltage 61 into the V0/VSL amplitude, and theresulting output signal 82 is input to the first logic circuit 64.

[0126] As shown in FIG. 6, two kinds of supply voltages, V0 and VSL, areinput to the first logic circuit 64, and the output signal from thelevel shift circuit 63 is processed by the logic circuit describedlater. The first logic circuit 64 can be constructed in variousconfigurations according to its purpose such as power consumptionreduction, but its simplest operation purpose is to switch the firstoutput driver circuit 65. Therefore, in its simplest configuration, itcan be constructed with a single buffer which switches between V0 andVSL.

[0127] The signal processed by the first logic circuit 64 is input tothe first output driver circuit 65. The first output driver circuit 65is supplied with two supply voltages V0 and VD2. Like the first logiccircuit 64, the first output driver circuit 65 can also be constructedin various configurations according to its purpose such as powerconsumption reduction, output impedance setting, etc. One example of thesimplest circuit configuration is shown in FIG. 9.

[0128]FIG. 9 is a circuit diagram showing one example of the firstoutput driver circuit in the configuration of FIG. 6. Reference numeral91 is a PMOS-FET, and 92 is an NMOS-FET. The source and bulk side of thePMOS-FET 91 is connected to the power supply line of V0, and its drainis connected to the drain of the NMOS-FET 92 whose source and bulk sideis connected to the power supply line of VD2. Further, reference numeral90 indicates the output signal of the first logic circuit 64.

[0129] When the output signal 90 from the first logic circuit 64 is V0,the NMOS-FET 92 in the first output driver circuit 65 conducts and VD2is output as the VDD 66, while when the output signal 90 is VSL, thePMOS-FET 91 conducts and V0 is output.

[0130] To recapitulate the operation of the first output block circuit62, when the reference signal is at VDL, VD2 is output as the VDD 66,and when the reference signal is at VSL, V0 is output as the VDD 66.

[0131] Next, the operation of the second output block circuit 67 will bedescribed with reference to FIG. 6. The second output block circuit 67comprises two circuit blocks 68 and 69, i.e., the second logic circuit68 and the second output driver circuit 69 constructed from anopen-drain circuit of a first PMOS-FET.

[0132] VDL and VSL are input to the second logic circuit 68 to which isalso input the reference signal 61 as a signal. The second logic circuit68 comprises, for example, several inverter stages, and morespecifically, an even number of inverter stages, as shown in the firsthalf of FIG. 10.

[0133] The output of the second logic circuit 68 is coupled to thesecond output driver circuit 69. The detailed circuit configuration ofthe second output driver circuit 69 is shown in the second half of FIG.10.

[0134]FIG. 10 shows one example of the circuit configuration of thesecond output driver circuit. Reference numeral 101 indicates aPMOS-FET. Reference numeral 100 is the output of the second logiccircuit 68, which is coupled to the gate of the PMOS-FET 101. The sourceand bulk side of the PMOS-FET 101 is connected to VDL. The drain of thePMOS-FET 101 is connected to the VCC 70; as a result, the VCC 70 is theopen-drain output of the PMOS-FET 101. The second logic circuit 68comprises, for example, inverters 102 and 103 to which the referencesignal 61 is input, as shown in the figure.

[0135] Accordingly, in the second output block circuit 67, when thereference signal 61 is at VDL, the PMOS-FET 101 is non-conducting andthe VCC 70 (see FIG. 6) is therefore put in a high impedance state; onthe other hand, when the reference signal 61 is at VSL, the PMOS-FET 101is conducting and the VCC 70 outputs VDL.

[0136] Next, the operation of the third output block circuit 71 will bedescribed with reference to FIG. 6. The third output block circuit 71comprises two circuit blocks 72 and 73, i.e., the clamping circuit 72for clamping the reference signal 61 and the third output driver circuit73 constructed from an open-drain circuit of a PMOS-FET. The detailedconfiguration will be described below.

[0137]FIG. 11 is a circuit diagram showing one example of the clampingcircuit forming part of the third output block circuit in theconfiguration of FIG. 6. The clamping circuit 72 is a circuit forclamping the reference signal 61 to VSL. Reference numeral 111 is acapacitor, 112 is a diode, and 113 is a first resistor. One terminal ofthe capacitor 11 is connected to the reference signal 61, and the otherterminal is connected to the cathode of the diode 112 as well as to oneend of the first resistor 113; the anode of the diode 112 and the otherend of the first resistor 113 are connected to the power supply line ofVSL.

[0138] Accordingly, in the clamping circuit 72, when the referencesignal 61 is at VDL, the diode 112 conducts and the reference signal 61is clamped to VSL; on the other hand, when the reference signal 61 is atVSL, the diode 112 does not conduct and the potential is held to -VDL,and the resulting signal is supplied to the third output driver circuit73.

[0139]FIG. 12 shows one example of the circuit configuration of thethird output driver circuit in the configuration of FIG. 6. Referencenumeral 121 indicates a PMOS-FET. The output 120 of the clamping circuit72 of FIG. 11 is coupled to the gate of the PMOS-FET 121. The source andbulk side of the PMOS-FET 121 is connected to VSL. The drain of thePMOS-FET 121 is the output which is supplied to the VSS 74. As a result,the VSS 74 is the open-drain output of the PMOS-FET 121.

[0140] Accordingly, in the third output block circuit 71, when thereference signal 61 is at VDL, the PMOS-FET 121 is non-conducting andthe VSS 74 is therefore put in a high impedance state; on the otherhand, when the reference signal 61 is at VSL, the PMOS-FET 121 isconducting and the VSS 74 outputs VSL.

[0141] The above has described the basic operation of the swinging powersupply integrated circuit 18 of the invention shown in FIG. 6. However,when actually using the swinging power supply integrated circuit 18 asthe power supply generating circuit employing the swinging power supplymethod, external capacitors must be connected.

[0142]FIG. 13 is a block diagram showing the external capacitorsconnected to the power supply generating circuit of the configurationshown in FIG. 6. In the figure, reference numeral 130 indicates thefirst capacitor, and 131 the second capacitor. One terminal of the firstcapacitor 130 is connected to the VDD 66, and the other terminal isconnected to the VSS 74. On the other hand, one terminal of the secondcapacitor 131 is connected to the VSS 74, and the other terminal isconnected to the VCC 70. The first capacitor 130 and the secondcapacitor 131 are both chosen to have a suitable capacitance accordingto the size of the panel used, the driving frequency, etc.

[0143]FIG. 14 is a diagram showing the swinging power supply waveformsgenerated by the swinging power supply integrated circuit of theconfiguration shown in FIG. 6. In the figure, reference numeral 140 isV0, 141 is VD2, 142 is VDL, and 143 is VSL. Further, 144 is thereference signal, 145 is VDD, 146 is VCC, and 147 is VSS.

[0144] For the outputs VDD (145), VCC (146), and VSS (147), when thereference signal 144 is at VDL, then VDD (145) 15 is at VD2 (146), VCC(146) is at (VDL-(V0-VD2)), and VSS (147) outputs the potential of(VSL-(V0-VD2)). When the reference signal 144 is at VSL, then VDD (145)is at V0 140, VCC (146) is at VDL, and VSS (147) outputs the potentialof VSL.

[0145] The power supply generation based on the swinging power supplymethod can thus be achieved by using the swinging power supplyintegrated circuit constructed as an integrated circuit having the abovecircuit configuration.

[0146]FIG. 15 is a circuit diagram showing one example of a dischargecircuit in the configuration of FIG. 6; the detailed configuration ofthe discharge circuit 75 shown in FIG. 6 is illustrated here. The powersupply lines of VDL, VSL, and VSS are connected to the discharge circuit75. Reference numeral 150 is a PMOS-FET, 151 is a resistor, 152 is aPMOS-FET, and 153 is a resistor. The source and bulk side of thePMOS-FET 150 is connected to VDL, and its gate is connected to VSL. Itsdrain is connected to the resistor 151 and the PMOS-FET 152. The sourceand bulk side of the PMOS-FET 152 is connected to VSL, and its drain isconnected to the resistor 153. One end of the resistor 151 and one endof the resistor 153 are both connected to VSS. Reference numeral 131indicates the external capacitor shown in FIG. 13.

[0147] When the whole system is in operation, that is, when VDL is beinginput, a potential difference greater than the Vth of the PMOS-FET 150,in this case, the potential difference between VDL and VSL, is beingapplied to the gate of the PMOS-FET 150, so that the PMOS-FET 150 isconducting. Here, the ratio of the ON resistance value of the conductingPMOS-FET 150 to the resistance value of the resistor 151 is adjusted soas to set the potential at the drain of the PMOS-FET 150 to a voltage atleast not smaller than VSL-Vth; therefore, a voltage greater than Vth isnot applied to the gate of the PMOS-FET 152, so that the PMOS-FET 152 isput in a non-conducting state. In this way, during the use of thesystem, VSL and VSS are prevented from conducting through the PMOS-FET152 and the resistor 153.

[0148] When the system is not in operation, that is, when power is cutoff, VDL drops toward VSL. When the potential of VDL drops below the Vthof the PMOS-FET 150, the PMOS-FET 150 is put in a non-conducting state.

[0149] When the PMOS-FET 150 is non-conducting, the drain potential ofthe PMOS-FET 150 becomes equal to VSS. Accordingly, VSS is applied tothe gate of the PMOS-FET 152. Here, if power is cut off when thereference signal is at VDL, since VSS is greater than the Vth of thePMOS-FET 152, the PMOS-FET 152 is immediately put in the conductingstate.

[0150] As a result, VSL and VSS conduct through the PMOS-FET 152 and theresistor 153, and the charge stored in the external capacitor 131 isdischarged, and VSS becomes substantially equal to the potential of VSL.The resistor 153 acts to prevent destruction of other devices bylimiting the current during the discharge, and its resistance need onlybe set to a suitable value.

[0151] With the above operation, even when the power is cut off duringthe selection operation of the scanning line driving circuit, as thedriving voltage being applied can be discharged by the action of thedischarge circuit, the DC component can be prevented from beingcontinuously applied.

[0152]FIG. 16 is a circuit diagram showing one example of the firstlogic circuit and the first output driver circuit forming the firstoutput block circuit in the configuration of FIG. 6. Here, referencenumeral 64 is the first logic circuit 64 in FIG. 6, and 65 is the firstoutput driver circuit 65.

[0153] In the first logic circuit 64, 160 indicates a buffer; the outputof the level shift circuit 63 shown in FIG. 6 is connected to the inputof the buffer 160. Reference numeral 161 is a first output selectioncircuit, and 162 is a second output selection circuit. Each outputselection circuit comprises one OR circuit and one AND circuit. That is,163 is the OR circuit and 164 is the AND circuit, which togetherconstitute the output selection circuit 161. Further, 165 is a firstoutput setting terminal, and 166 is a second output setting terminal. Onthe other hand, reference numerals 167 and 168 indicate inverters; theinput of the inverter 167 is connected to the first output settingterminal 165. The input of the inverter 168 is connected to the secondoutput setting terminal 166.

[0154] One input of the OR circuit 163 in the first output selectioncircuit 161 is connected to the first output setting terminal 165, andthe other input is connected to the output of the buffer 160. Similarly,one input of the AND circuit 164 in the first output selection circuit161 is connected to the output of the inverter 167, and the other inputis connected to the output of the buffer 160. To the second outputselection circuit 162 are connected the second output setting terminal166 instead of the first output setting terminal 165, and the output ofthe inverter 168 instead of the output of the inverter 167; otherwise,the configuration is exactly the same.

[0155] Next, the configuration of the first output driver circuit 65will be described. Reference numeral 169 is a first output driver, and170 is a second output driver. Basically, the first output driver 169and the second output driver 170 each have the configuration shown inFIG. 9. In the configuration of FIG. 9, the PMOS-FET and the NMOS-FETare coupled together by their gates, to which the output 90 from thefirst logic circuit 64 is input, but in the configuration of FIG. 16,their gates are connected to the outputs of the OR circuit and the ANDcircuit, respectively. One the other hand, the output of the firstoutput driver 169 and the output of the second output driver 170 arecoupled together to provide the VDD 66.

[0156] As described above, the output of the OR circuit 163 in the firstoutput setting circuit 161 is connected to the gate of the PMOS-FET inthe first output driver 169, and the output of the AND circuit 164 isconnected to the gate of the NMOS-FET. The outputs of the second outputsetting circuit 162 are connected to the second output driver 170 inlike manner.

[0157] Next, a description will be given for the case where the firstoutput setting terminal 165 and the second output setting terminal 166are both at the high level. As already explained, in the first logiccircuit 64, the logic signal level is high when it is V0, and low whenVSL.

[0158] When the first output setting terminal 165 is at the high level,the output of the OR circuit 163 is high and the output of the ANDcircuit 164 is low, regardless of whether the input to the buffer 160 ishigh or low. As a result, the output of the first output driver 169 isin a high impedance state, and the second output driver 170 alsoexhibits a similar state.

[0159] Next, a description will be given for the case where the firstoutput setting terminal 165 and the second output setting terminal 166are both at the low level. When the first output setting terminal 165 isat the low level, if the input to the buffer 160 is high, the output ofthe OR circuit 163 and the output of the AND circuit 164 are both high.As a result, the NMOS-FET is selected as the output of the first outputdriver 169, and VD2 is thus output.

[0160] If the input to the buffer 160 is low, the output of the ORcircuit 163 and the output of the AND circuit 164 are both low. As aresult, the PMOS-FET is selected as the output of the first outputdriver 169, and V0 is thus output. The second output driver 170 issimilar in operation.

[0161] Here, consider the case where the first output setting terminal165 is at the low level and the second output setting terminal 166 is atthe high level. In this case, the first driver 169 outputs V0 or VD2,depending on the input polarity of the reference signal. However, theoutput of the second driver 170 is in the high impedance state,regardless of the input polarity of the reference signal. By so doing,the output impedance can be reduced to one half, compared with theimpedance when the first output setting terminal 165 and the secondoutput setting terminal 166 are both at the low level. Accordingly,since the output impedance can be adjusted to an optimum level accordingto the display panel size, etc. by using the same chip, the impedancedoes not become lower than necessary, and thus the shoot-through currentas well as the power consumption can be reduced. In the presentinvention, only two output settings are provided, but in the case ofthree or more output settings, a similar configuration to the onedescribed above can be employed, in which case a more precise settingcan be achieved.

INDUSTRIAL APPLICABILITY

[0162] When the power supply generating circuit employing the swingingpower supply method is constructed in integrated circuit form andincorporated in the liquid crystal display apparatus, as in the presentinvention, the power consumption, the size, and the cost can be reduced,and besides, many advantages are offered in design and fabrication andthe product reliability improves; therefore, the industrialapplicability is extremely high.

LIST OF REFERENCE NUMERALS

[0163]10 . . . LIQUID CRYSTAL PANEL

[0164]11 . . . DATA LINE

[0165]13 . . . SCANNING LINE

[0166]14 . . . LOWER GLASS SUBSTRATE

[0167]15 . . . SCANNING LINE DRIVING CIRCUIT

[0168]16 . . . UPPER GLASS SUBSTRATE

[0169]17 . . . DATA LINE DRIVING CIRCUIT

[0170]18 . . . SWINGING POWER SUPPLY INTEGRATED CIRCUIT

[0171]19 . . . FPC

[0172]21 . . . REFERENCE VOLTAGE GENERATING CIRCUIT

[0173]22 . . . STEP-UP CIRCUIT

[0174]23 . . . CAPACITOR

[0175]31, 32, 33, 34 . . . FIRST TO FOURTH FETs

[0176]35, 36, 41 . . . FIFTH TO SEVENTH FETs

[0177]61 . . . REFERENCE SIGNAL

[0178]62 . . . FIRST OUTPUT BLOCK CIRCUIT

[0179]63 . . . LEVEL SHIFT CIRCUIT

[0180]64 . . . FIRST LOGIC CIRCUIT

[0181]65 . . . FIRST OUTPUT DRIVER CIRCUIT

[0182]67 . . . SECOND OUTPUT BLOCK CIRCUIT

[0183]68 . . . SECOND LOGIC CIRCUIT

[0184]69 . . . SECOND OUTPUT DRIVER CIRCUIT

[0185]71 . . . THIRD OUTPUT BLOCK CIRCUIT

[0186]72 . . . CLAMPING CIRCUIT

[0187]73 . . . THIRD OUTPUT DRIVER CIRCUIT

[0188]75 . . . DISCHARGE CIRCUIT

1. (Deleted)
 2. (Deleted)
 3. (Amended) A liquid crystal displayapparatus comprising: a liquid crystal panel constructed by sandwichinga liquid crystal between a first transparent substrate having aplurality of data lines and a second transparent substrate having aplurality of scanning lines crossing said data lines; a data linedriving integrated circuit connected to said plurality of data lines;and a scanning line driving integrated circuit for driving saidplurality of scanning lines, wherein said data line driving integratedcircuit is mounted on said first transparent electrode substrate, andsaid scanning line driving integrated circuit is mounted on said secondtransparent substrate, and wherein an swinging power supply integratedcircuit for swinging a power supply potential of said scanning linedriving integrated circuit while maintaining a constant amplitude inresponse to a liquid crystal driving AC signal is provided which ismounted directly on said second transparent substrate, and said swingingpower supply integrated circuit is constructed from a single chip, andtakes as inputs said liquid crystal driving AC signal and an output of astep-up circuit that defines the amplitude of said swinging powersupply.
 4. (Amended) A liquid crystal display apparatus as set forth inclaim 3, wherein said swinging power supply integrated circuitcomprises: three output block circuits consisting of a first outputblock circuit, a second output block circuit, and a third output blockcircuit; and one discharge block circuit, and wherein said first outputblock circuit comprises: a level shift circuit which converts theamplitude of an externally supplied reference signal into a prescribedamplitude; a first logic circuit which controls the timing of saidreference signal whose level has been converted by said level shiftcircuit; and a first output driver circuit which delivers an output ofsaid first logic circuit, said second output block circuit comprises: asecond logic circuit which controls the timing of said reference signal;and a second output driver circuit which outputs a value of said secondlogic circuit, said third output block circuit comprises: a clampingcircuit which clamps said reference signal; and a third output drivercircuit which outputs a value of said clamping circuit, and saiddischarge block circuit comprises: a detection circuit which detects asystem power supply being turned off; and a discharge circuit whichshort-circuits said third output driver circuit by a signal detected bysaid detection circuit.
 5. (Amended) A liquid crystal display apparatusas set forth in claim 3, wherein said swinging power supply integratedcircuit comprises: three output block circuits consisting of a firstoutput block circuit, a second output block circuit, and a third outputblock circuit; and one discharge block circuit, and wherein said firstoutput block circuit comprises: a level shift circuit which converts theamplitude of an externally supplied reference signal into a prescribedamplitude; a first logic circuit which controls the timing of saidreference signal whose level has been converted by said level shiftcircuit; and a first output driver circuit constructed from an inverterwhose gate is connected to a signal output from said first logiccircuit, said second output block circuit comprises: a second logiccircuit which controls the timing of said reference signal; and a secondoutput driver circuit constructed from an open-drain circuit of a firstPMOS-FET whose gate is connected to a signal output from said secondlogic circuit, said third output block circuit comprises: a clampingcircuit which clamps said reference signal; and a third output drivercircuit constructed from an open-drain circuit of a second PMOS-FETwhose gate is connected to a signal output from said clamping circuit,and said discharge block circuit comprises: a detection circuit whichdetects a system power supply being turned off; and a discharge circuitwhich short-circuits said third output driver circuit by a signaldetected by said detection circuit.
 6. (Amended) A liquid crystaldisplay apparatus as set forth in claim 5, wherein said clamping circuithas a configuration such that one end of a capacitor is connected tosaid supplied reference signal and the other end thereof is connected toa cathode of a first diode, one end of a first resistor, and the gate ofsaid second PMOS-FET, while an anode of said first diode and the otherend of said first resistor are connected to a source and bulk of saidsecond PMOS-FET.
 7. (Amended) A liquid crystal display apparatus as setforth in claim 5, wherein said discharge block circuit has a circuitconfiguration such that a source and bulk of a third PMOS-FET areconnected to a source and bulk of said first PMOS-FET, a gate of saidthird PMOS-FET is connected to a source and bulk of said secondPMOS-FET, and a drain of said third PMOS-FET is connected to a gate of afourth PMOS-FET and a second resistor, while a source and bulk of saidfourth PMOS-FET are connected to the source and bulk of said secondPMOS-FET and a drain of said fourth PMOS-FET is connected to a thirdresistor whose one end is connected to said second resistor and a drainof said second PMOS-FET.
 8. A liquid crystal display apparatus as setforth in claim 4 or 5, wherein said first output block circuit comprisesa plurality of PMOS-FETs and a plurality of NMOS-FETs, and wherein anoutput selection circuit having a function that can always turn off partof said plurality of PMOS-FETs and part of said plurality of NMOS-FETsby an external output setting terminal independently of said referencesignal is provided at a gate input of each of said PMOS-FETs and saidNMOS-FETs.